The present disclosure relates to signal processing in radio receivers and in particular to an automatic gain control (AGC) system and method in which the effects of DC current transients on system performance are reduced.
Reception of radio signals in a radio apparatus configured therefore and down converting the desired receiving signal from the radio frequency (RF) band into the baseband can generally be done in different ways. A common way is to convert the RF signal down to an intermediate frequency (IF) and in a second step to convert the resulting signal down into the baseband. The converting operation is usually done by a well-known mixing operation with a suitable mixing frequency.
For cost reduction, in zero IF receivers, which are broadly used in wireless systems, down conversion from the RF receiving signal to the baseband is done directly without the intermediate frequency step. One drawback in zero-IF receivers is the presence of a residual direct current (DC) offset after the down conversion of the receiving signal, wherein self-mixing of the local oscillators and/or second order intermodulation of the employed mixers creates DC offsets in the baseband signal. Further, even-order distortions may convert strong interfering signals to baseband. Furthermore, 1/f noise being inherent in all semiconductor devices and being inversely proportioned to the frequency (f) may mask the baseband signal. Moreover, direct conversion receivers put high demands on the baseband signal processing components because gain control and filtering must be done at baseband frequency range.
In modern receiver architectures, the analog RF receiving signal is converted from the analog domain into the digital domain for further processing, since digital signal processing is available with high performance and at low cost. In order to match the signal dynamics required by the system before and after the used analogue-to-digital converters (ADC), an automatic gain control (AGC) system could be used for control of amplification gain for the receiving signal in the one or more signal amplifiers located in the reception path.
The DC offset may be quite large causing saturation of the ADC, e.g. leading to loss of dynamics, and other problems in the receiver. To cope with these effects, so called DC offset compensation circuits are generally employed in the reception (RX) path of radio receivers. Basically, a simple example for DC offset cancellation is application of capacitors, connected in series into the signal path and thus blocking propagation of DC signals. A more complex approach is an active high pass filter configured to remove the unwanted DC components inherent to self-mixing products.
Usually, AGC is implemented by a respective gain control algorithm. Due to the digital nature of most AGC systems, also the analogue gain, i.e. in the receiving path before the ADC, is adjusted by changing the gain of the respective amplifiers in a stepwise manner, i.e. the gain is controlled in discrete gain steps. However, switching of the gain in the signal path generates DC transients in the DC offset, which from a frequency spectrum point of view contain higher frequency components, which cannot be filtered or cancelled by the DC offset compensation or cancellation circuits.
Thus, even that the DC compensation is permanently active, DC transients occur at gain step transitions; every time these gain steps are toggled. Moreover, these transients are heavily RF architecture dependent. Their settling time and peak voltage depend on a variety of RF IC architecture parameters, such as the impedance of the receiving gain chain, the location of the AGC loops with regards to amplifier gain locations and the weight of the gain step.
For instance, link level simulations for UMTS release 5, HSDPA, have shown that DC transients in the order of the frame rate caused by the AGC loop degrade the throughput versa system performance of baseband (BB) integrated circuit (IC), e.g. the signal to noise ratio (SNR).
US 2005/0208916 A1 discloses a direct down conversion receiver architecture comprising a digital variable gain amplifier (DVGA), an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus.
US 2003/0199264 A1 discloses a system and method for a fast acquiring DC offset cancellation by increasing high pass loop bandwidth and adjusting DC offset levels at baseband. Afterwards the high pass loop bandwidth is decreased in order to fine-tune the previous estimate and to remove small variation in DC.